architecture

CPU for MIPS: ORI's Five-Stage Pipeline

arkts

ArkTS: Analyze Riscv64 Assember

ArkTS: Compile Runtime_core and Ets_*

ArkTS: Analyze Compiler_assembler

cephv10.2.1

CephV10.2.1: Deploy Ceph

CephV10.2.1: Overall Architecture

CephV10.2.1: Universal Modules

books

Concurrency in Action: Introduction

Concurrency in Action: Managing Threads

Concurrency in Action: Share Data Between Threads

DDCA: The Chapter 2 Reading

DDCA: The Chapter 1 Reading

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leveldb

LevelDB: A Whole Open Operation

LevelDB: A Whole Put Operation

cpp

STL17: New Features

rfc

Rfc1951: DEFLATE Compressed Data Format Specification

Rfc1952: GZIP File Format Specification

raft

Raft: An Understandable Consensus Algorithm

xv6

Xv6: The Kernel Env

Xv6: The Spin Lock

Xv6: The Starter

Xv6: The Boot Loader

Xv6: The Uart

rCore

rCore Ch3 Details